In-line wafer back grinding uses an automatic control system (ACS) and a high-level diagram of the process flow. Various methods are used to hold a semiconductor wafer on the chuck table 110. Suction or a physical clipping mechanism is an example of a suitable holding mechanism. Other methods are also effective and are not shown for clarity. The ACS also controls the process in real-time. A semiconductor wafer 20 is place on a chuck table 110 and held on the chuck table 110.
A typical wafer back-grinding process involves placing a wafer on a chuck table and removing the excess substrate by grinding it. The back-grinding process can be performed sequentially or in parallel, with multiple wafers processed at the same time. Controls for this process usually involve measuring related parameters. Current can be measured with the spinel of the grinding wheel, which reflects the friction between the wheel and the wafer. The capacitance of the grinding wheel can also be measured to measure the back-grinding process.
Before the actual grinding process, the wafer film is thin with the dicing tape. The die is then package in a mylar frame, often in Gel-Paks(r), tape and reel packaging, or directly onto a print circuit board.
Equipment used in back-grinding
There are several pieces of equipment use in wafer back-grinding. One such machine is known as a thin wafer lamination machine, which is use to attach a thin wafer to a tape and grind the back side of the wafer. This equipment is also use to separate chips and is one of the front-end pieces of equipment used in wafer back-grinding. This type of equipment is usually automate and is operate by a robotic arm.
Wafer back-grinding equipment requires highly accurate measurements to get the precise removal of material. The equipment can remove material up to 100-um thick, including logic gates, DRAM memory, and MEMS memories. Manufacturers often request high-resolution measurements from their suppliers before shipping their wafers, and many may also measure them upon receipt to ensure accuracy. This is where equipment like MTI Instruments comes into play.
Impact on wafer’s surface
The impact of back grinding on the surface of a wafer is studied in this paper. The main objective of the study is to identify the parameters that affect the grain-to-wafer contact area and their respective mechanical effects. To do this, a theoretical 3D surface topography simulation model was develop to evaluate the process of material removal and generation at the grinding zone. The model includes multiple grinding parameters, grain randomness, plastic side flow, and brittle fracture to describe the process’s effects on the surface.
In addition to the physical appearance of the surface, back-ground silicon wafers display a scratch pattern. The size of the grit used and the vertical pressure applied during grinding determine the depth of the scratches. Deep scratches have a lower strength than shallower ones, but deep scratches are more easily visible in the back side. Backside surface roughness directly correlates with the strength of a semi-conductor die. It is therefore critical to produce the smoothest backside surface possible.
Problems with bumps on the front side of the wafer
If you want to produce semiconductor devices with bumps on the front side, you should be aware of these issues. These bumps reduce the overall thickness of the wafer, making them potential stress concentration points. In addition to reducing overall thickness. Bumps on the front side of the wafer also increase the risk of wafer breakage. In order to prevent bumps from disrupting the fabrication process, you can apply laser-resistant dicing tape.
The process of dicing wafers with bumps on the front side can be problematic. The particularly for hybrid structures made of a logic chip and a memory die. Bumps on the backside of the wafer are connect to the substrate by a solder strip. The bumps on the front side of the wafer may prevent the wafer from being slice using conventional blade saws or laser full thickness dicing methods.